1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and more particularly, to a method for wet etching of high k thin film at low temperature.
2. Description of Relative Prior Art
The recent development of semiconductor such as CMOS logic device or dynamic random access memory (DRAM), is preferable to increase the integration, increase the capacity, decrease the driving voltage etc., to meet the requirement of high speed, less delay. The design rule is more and more quickly reduced. It is a result that the thickness of the gate oxide is decreasing and approaching 60A or less. The fabrication process is more difficult to control. In a capacitor of a DRAM, a silicon dioxide insulator or an oxide-nitride-oxide (ONO) can not satisfy the need of the memory charge capacity, it is a trend that high dielectric film is used as the insulating film of a capacitor to replace the silicon dioxide or ONO. Recently, as the design rule approach 0.18 μm, there are lots of gate dielectric material can be used. The main requirement is: high dielectric, low leakage current, easy to etch and less contamination to the active area, etc. The most preferred material is Hafhium oxide (HfO2) or Zirconium oxide (ZrO2). Although they have an idea dielectric constant of 15-25, and more stable that they do not diffuse into the silicon active area, and the leakage current is less, but it is not easy to be etched. The experiment data is shown in Table 1.
TABLE 1ChemicalEtch rate of HfO2 (A/min)Pure HClO40.3Pure H2SO4(at 160° C.)1.25-5.25Pure H3PO4(at 80° C.)0BOE20Pure (COOH)20-2Pure HCl  0-0.9Pure HBr2.5-10 Pure HI0Pure HF101Pure H2O20TMAH0.4
From Table 1, we know that etching with Sulfuric acid (H2SO4) need to heat up to 160° C. and the etch rate is only 5A/min, the others like Phosphoric acid (H3PO4), acitic acid (COOH)2, Hydrochloric acid (HCl), Hydro Bromide acid (HBr), Hydro iodine acid (HI), and pure HClO4, has etch rate near zero. Although BOE and HF has etch rate of 20A/min and 100A/min respectively, but cannot be used since they also etch silicon dioxide. Poor selectivity of dry etching causes leakage current, which due to defects on the surface of the source/drain. So it needs to develop a new technique to replace wet etching by hot sulfuric acid and dry etching techniques.
FIG. 1 shows the cross section view before etching the gate dielectric of a CMOS device using Hafnium oxide (HfO2) as the gate dielectric. Isolation 4 is formed on a silicon wafer 1 by LOGOS or STI, then using lithography and ion implantation to form a p-well 2 and n-well 3, after deposited Hafnium oxide film 5, poly-Si 6 and tungsten silicide or other silicide 7 formed a gate 9, the Hafnium oxide is now using as the etch stop. Then by using lithography and ion implantation to form a lightly doped n− source/drain area 10 and p− source/drain area 11. Refer to FIG. 2, by using lithography and ion implantation technique to form heavily doped n+ and p+ source/drain 12,13, thus form a LDD structure. Now the hafnium oxide has not etched away and is used as the buffer layer of ion implantation to prevent defects form on the surface of silicon. Finally, by using dry etching to remove the hafhium oxide above the source/drain area. The un-doped silicon glass (USG) and the silicon above the source/drain may form defects 14 since the selectivity is not high enough. After the process is completed the leakage current of the device will increase. The same reason is applied to the etching of the dielectric film of a DRAM, it may hurt the lower electrode and inter-metal-dielectric (IMD). Alternatively, if we use wet etching by hot sulfuric acid, the selectivity is good, but the etch rate is very low and need high temperature endurable equipments. It is preferred to develop a wet etch method at low temperature to improve the yield of production.